Digital Traffic Light Controller

Engineered a demand-driven traffic signal controller designed to manage an intersection between a high-traffic main road and a pedestrian crosswalk. The system prioritizes the main road with a default green light, only initiating a state change sequence when a pedestrian manually queues a crossing request.

SYSTEM ARCHITECTURE & LOGIC DESIGN

Designed a four-state machine that safely transitions the intersection through standard traffic light protocols at a precise 0.25 Hz frequency. Developed state transition tables and excitation equations to determine the necessary logic gates. Built the physical circuit on a breadboard using dual D flip-flops to manage state memory, alongside a network of XOR, AND, NOT, NAND, and OR gates. Successfully interfaced the custom logic board with a physical, scaled traffic light model utilizing TTL logic level inputs and a 10-pin adapter cable.

CLOCK GENERATION

Configured an LM555 timer integrated circuit in astable mode to act as the primary clock generator for the D flip-flops. Utilized a precise combination of 1k ohm and 27k ohm resistors paired with 100 µF and 0.01 µF capacitors to manipulate the internal comparators of the timer, achieving the exact 4-second state duration required for the intersection.

SYSTEM RELIABILITY / FAILURE MODES

Troubleshooting & Safety Analysis

Overcame critical memory retention issues during the physical build by systematically tracing connections with a logic probe, eventually isolating and replacing a faulty AND gate chip. Conducted a system failure analysis on brief power outages, identifying a critical flaw where a power reset would force an immediate return to the default state (Main Road Green). Proposed and documented a fail-safe implementation requiring an auxiliary fifth state (All Red) upon boot to protect pedestrians mid-crosswalk during an outage.

FAIL-SAFE BOOT PROPOSAL: ALL RED → VERIFIED SAFE STATE → NORMAL OPERATION